One of the most confusing things to me about VHDL is that the <= operator can mean both "less than or equal to" and it can be a signal assignment operator. When it means "less than or equal to", it is, of course, left-associative. But when it is a signal assignment operator, it is, of course, right-associative. So, how can it be parsed?
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General ways to resolve this kind of ambiguity:
- Context-free then rewrite: the nodes for both operations are initially parsed into a common AST node type, then a rewrite step somewhere in the pipeline fixes them. For instance, all
<=are initially parsed as less-than-or-equal-to operations with left associativity, but when a statement block is parsed, its constructor rewrites all inner<=into signal assignment operations, and re-parents them to make them right-associative.
- Context-sensitive: the AST could be parsed using recursive-descent or another algorithm which intrinsically supports context-sensitivity. In a recursive descent parser, there is a function for every AST node type that parses just nodes of that type, and these functions parse child nodes by calling the respective parser for their type. The statement parser can call a different parser for
<=operations then the expression parser.
For this specific case, I'm not familiar with VHDL, but some languages don't support composing less-than-or-equal operations at all, so a <= b in expressions has no associativity. bool1 <= bool2 is just another way of writing !bool1 || bool2, and the latter is almost always clearer, so some languages make <= on booleans illegal; since <= evaluates to a boolean, it follows that a <= b <= c in an expression is also illegal. If this is the case, then one can parse all <= operations as right-associative.
=for assignment and equality? What does using this operator look like concretely? $\endgroup$a <= b <= c <= ... <= xof arbitrary length, and then determine its meaning later. I don't know VHDL, but in general if<=has multiple meanings but only at most one meaning in each lexical position (e.g.=might mean assignment in a statement or equality in a condition, as Michael Homer suggests) then it can be parsed differently in each of those positions. Are there any examples in VHDL where<=really could mean either depending on something other than the position it appears in the source code? $\endgroup$a <= b <= cbut this is neither left- nor right-associative, it really meansa <= b && b <= c(but without evaluatingbtwice). $\endgroup$