There's two questions into one here:
Would a structure ever require padding beyond what is required to align the members?
Maybe? That is an implementation detail, and C tells you it doesn't care about it.
Also you would need to expand on what you mean by "required to align the members." Required by RAM? The I/O bus? The memory bus? Cache lines? Registers? They all can have different requirements!
Is there any reason to permit arbitrary (seemingly meaningless) padding?
Now why does C word this to leave it as an implementation detail?
C makes such liberal choices because it was written at a time when "consumer hardware" was virtually non-existant, and business machines had no international standards on their memory addressing and object sizing mechanisms.
Remember C was written for the PDP-11 which has its own endianness - objects laid out with the most significant word first, and words laid out with the least significant byte first - and whose predecessor, the PDP-8, has 12 bits addressable bytes, and 6 bits characters.
This kind of historical decisions is also why the size of C characters is implementation-defined, with the requirement that all "valid" characters be non-negative even when in signed objects, limiting them to 7 bits in machines with 8 bits addressable bytes like x86, amd64 or ARM, with the possible 1bit extension for sign left as an implementation detail.
Even in today's, "consumer hardware," some operating systems such as Windows CE have toolchains with minimal 16bits-aligned addressing.
C must be compatible with all those machines.
This is why C23§126.96.36.199.1. says
The representations of all types are unspecified [...]., why §188.8.131.52. says
An alignment is an implementation-defined integer value representing the number of bytes between successive addresses at which a given object can be allocated, and why §184.108.40.206.5. says
The value of the result of [the sizeof and alignof] operators is implementation-defined.
C code must be able to run on a machine where RAM has 18bits bytes, characters are 6bits, the memory bus is 24bits, and registers are 32bits, and where load instructions only accept multiples of 18 up to 108.
Oh, also did you know x86 has a sub-ISA with bit addresses?